Solid-State Electronics

Solid-State Electronics, Vol.58, No.1 Entire volume, number list

ISSN: 0038-1101 (Print)

In this Issue (14 articles)

1 - 1	Special Issue Devoted to the 2nd International Memory Workshop (IMW 2010) Foreword Deleruyelle D, Iannaccone G
2 - 10	Post-manufacturing, 17-times acceptable raw bit error rate enhancement, dynamic codeword transition ECC scheme for highly reliable solid-state drives, SSDs Tanakamaru S, Fukuda M, Higuchi K, Esumi A, Ito M, Li K, Takeuchi K
11 - 16	Impact of Ge-Sb-Te compound engineering on the set operation performance in phase-change memories Boniardi M, Ielmini D, Tortorelli I, Redaelli A, Pirovano A, Allegra M, Magistretti M, Bresolin C, Erbetta D, Modelli A, Varesi E, Pellizzer F, Lacaita AL, Bez R
17 - 22	A fast and reliable method used to investigate the size-dependent retention lifetime of a phase-change line cell Goux L, Hurkx GAM, Wang XP, Delhougne R, Attenborough K, Gravesteijn D, Wouters D, Gonzalez JP
23 - 27	Empirical investigation of SET seasoning effects in Phase Change Memory arrays Zambelli C, Chimenton A, Olivo P
28 - 33	Highly-scalable disruptive reading and restoring scheme for Gb-scale SPRAM and beyond Takemura R, Kawahara T, Ono K, Miura K, Matsuoka H, Ohno H
34 - 41	A 1.0 V power supply, 9.3 GB/s write speed, Single-Cell Self-Boost program scheme for high performance ferroelectric NAND flash SSD Miyaji K, Node S, Hatanaka T, Takahashi M, Sakai S, Takeuchi K
42 - 47	Control of filament size and reduction of reset current below 10 mu A in NiO resistance switching memories Nardi F, Ielmini D, Cagli C, Spiga S, Fanciulli M, Goux L, Wouters DJ
48 - 53	Flexible and transparent ReRAM with GZO memory layer and GZO-electrodes on large PEN sheet Kinoshita K, Okutani T, Tanaka H, Hinoki T, Agura H, Yazawa K, Ohmi K, Kishida S
54 - 61	Demonstration of Conductive Bridging Random Access Memory (CBRAM) in logic CMOS process Gopalan C, Ma Y, Gallo T, Wang J, Runnion E, Saenz J, Koushan F, Blanchard P, Hollmer S
62 - 67	Comparative study of non-polar switching behaviors of NiO- and HfO2-based oxide resistive-RAMs Jousseaume V, Fantini A, Nodin JF, Guedj C, Persico A, Buckley J, Tirano S, Lorenzi P, Vignon R, Feldis H, Minoret S, Grampeix H, Roule A, Favier S, Martinez E, Calka P, Rochat N, Auvert G, Barnes JP, Gonon P, Vallee C, Perniola L, De Salvo B
68 - 74	Investigation of charge-trap memories with AlN based band engineered storage layers Molas G, Colonna JP, Kies R, Belhachemi D, Bocquet M, Gely M, Vidal V, Brianceau P, Martinez E, Papon AM, Licitra C, Vandroux L, Ghibaudo G, De Salvo B
75 - 82	Modeling of program, erase and retention characteristics of charge-trap gate all around memories Nowak E, Perniola L, Ghibaudo G, Molas G, Reimbold G, De Salvo B, Boulanger F
83 - 95	Low power options for 32 nm always-on SRAM architecture Hamouche L, Allard B