Solid-State Electronics

Solid-State Electronics, Vol.48, No.4 Entire volume, number list

ISSN: 0038-1101 (Print)

In this Issue (17 articles)

495 - 496	ULIS 2003 conference - Foreword Selmi L
497 - 503	CMOS downsizing toward sub-10 nm Iwai H
505 - 509	Towards the limits of conventional MOSFETs: case of sub 30 nm NMOS devices Bertrand G, Deleonibus S, Previtali B, Guegan G, Jehl X, Sanquer M, Balestra F
511 - 519	Single, double and surround gate vertical MOSFETs with reduced parasitic capacitance Gili E, Kunz VD, de Groot CH, Uchino T, Ashburn P, Donaghy DC, Hall S, Wang Y, Hemment PLF
521 - 527	Impact of technology parameters on device performance of UTB-SOI CMOS Schulz T, Pacha C, Luyken RJ, Stadele M, Hartwich J, Dreeskornfeld L, Landgraf E, Kretz J, Rosner W, Specht M, Hofmann F, Risch L
529 - 534	Subthreshold behavior of triple-gate MOSFETs on SOI material Lemme MC, Mollenhauer T, Henschel W, Wahlbrink T, Baus M, Winkler O, Granzner R, Schwierz F, Spangenberg B, Kurz H
535 - 542	Coupling effects and channels separation in FinFETs Dauge F, Pretet J, Cristoloveanu S, Vandooren A, Mathew L, Jomaah J, Nguyen BY
543 - 549	Comparative analysis of the RF and noise performance of bulk and single-gate ultra-thin SOI MOSFETs by numerical simulation Eminente S, Alessandrini M, Fiegna C
551 - 559	Performance evaluation of ultra-thin gate-oxide CMOS circuits Marras A, De Munari I, Vescovi D, Ciampolini P
561 - 566	Electrical analysis of external mechanical stress effects in short channel MOSFETs on (001) silicon Gallon C, Reimbold G, Ghibaudo G, Bianchi RA, Gwoziecki R
567 - 574	Atomic-scale modeling of double-gate MOSFETs using a tight-binding Green's function formalism Bescond M, Autran JL, Munteanu D, Lannoo M
575 - 580	Full-band approaches to the electronic properties of nanometer-scale MOS structures Sacconi F, Povolotskyi M, Di Carlo A, Lugli P, Stadele M
581 - 587	Modelling and simulation challenges for nanoscale MOSFETs in the ballistic limit Curatola G, Fiori G, Iannaccone G
589 - 595	Development of an analytical mobility model for the simulation of ultra-thin single- and double-gate SOI MOSFETs Alessandrini M, Esseni D, Fiegna C
597 - 608	DC and AC MOS transistor modelling in presence of high gate leakage and experimental validation Gilibert F, Rideau D, Bernardini S, Scheer P, Minondo M, Roy D, Gouget G, Juge A
609 - 615	On the extraction of the channel current in permeable gate oxide MOSFETs Palestri P, Esseni D, Guegan G
617 - 625	An effective model for analysing tunneling gate leakage currents through ultrathin oxides and high-k gate stacks from Si inversion layers Govoreanu B, Blomme P, Henson K, Van Houdt J, De Meyer K