Solid-State Electronics

Solid-State Electronics, Vol.47, No.7 Entire volume, number list

ISSN: 0038-1101 (Print)

In this Issue (20 articles)

1131 - 1131	3rd International Workshop on Ultimate Integration of Silicon - March 7-8, 2002, Munich, Germany - Foreword Risch L
1133 - 1139	Strained SiCMOS (SS CMOS) technology: opportunities and challenges Rim K, Anderson R, Boyd D, Cardone F, Chan K, Chen H, Christansen S, Chu J, Jenkins K, Kanarsky T, Koester S, Lee BH, Lee K, Mazzeo V, Mocuta A, Mocuta D, Mooney PM, Oldiges P, Ott J, Ronsheim P, Roy R, Steegen A, Yang M, Zhu H, Ieong M, Wong HSP
1141 - 1145	Quantum corrections in the simulation of decanano MOSFETs Asenov A, Brown AR, Watling JR
1147 - 1153	Characterization of effective mobility by split C(V) technique in N-MOSFETs with ultra-thin gate oxides Lime F, Guiducci C, Clerc R, Ghibaudo G, Leroux C, Ernst T
1155 - 1160	Static and low frequency noise characterization in surface- and buried-mode 0.1 mu m PMOSFETS Fadlallah M, Ghibaudo G, Jomaah J, Guegan G
1161 - 1165	The impact of short channel and quantum effects on the MOS transistor mismatch Difrenza R, Llinares P, Ghibaudo G
1167 - 1171	A new model for the current factor mismatch in the MOS transistor Difrenza R, Llinares P, Ghibaudo G
1173 - 1177	High performance Si/SiGe pMOSFETs fabricated in a standard CMOS process technology Collaert N, Verheyen P, De Meyer K, Loo R, Caymax M
1179 - 1182	High frequency n-type MODFETs on ultra-thin virtual SiGe substrates Hackbarth T, Herzog HJ, Rinaldi F, Soares T, Hollander B, Mantl S, Luysberg M, Fichtner PFP
1183 - 1186	Fabrication of Schottky barrier MOSFETs on SOI by a self-assembly COSi2-patterning method Zhao QT, Kluth P, Winnerl S, Mantl S
1187 - 1192	Simulation of the Esaki-tunneling FET Wang PF, Nirschl T, Schmitt-Landsiedel D, Hansch W
1193 - 1198	Simulation and optimization of EJ-MOSFETs Kittler M, Granzner R, Schwierz F, Henschel W, Wahlbrink T, Kurz H
1199 - 1203	Design considerations for fully depleted SOI transistors in the 25-50 nm gate length regime Luyken RJ, Schulz T, Hartwich J, Dreeskornfeld L, Stadele M, Rosner W
1205 - 1211	Evaluation of circuit performance of ultra-thin-body SOICMOS Pacha C, Schmal A, Schulz T, Gottsche R, Steinhogl W
1213 - 1218	Shrinking from 0.25 down to 0.12 mu m SOICMOS technology node: a contribution to low-frequency noise in partially depleted N-MOSFETs Dieudonne F, Haendler S, Jomaah J, Balestra F
1219 - 1225	Two-dimensional modeling of quantum ballistic transport in ultimate double-gate SOI devices Munteanu D, Autran JL
1227 - 1231	Ag metallization with high electromigration resistance for ULSI Hauder M, Hansch W, Gstottner J, Schmitt-Landsiedel D
1233 - 1236	Electrical characterization of copper interconnects with end-of-roadmap feature sizes Schindler G, Steinlesberger G, Engelhardt M, Steinhogl W
1237 - 1241	Processing technology for the investigation of sub-50 nm copper damascene interconnects Steinlesberger G, Engelhardt M, Schindler G, Kretz J, Steinhogl W, Bertagnolli E
1243 - 1248	Impact of parasitic elements on the performance of digital CMOS circuits with Gigabit feature size Schwantes S, Gottsche R, Krautschneider W