Solid-State Electronics
Solid-State Electronics, Vol.52, No.9 Entire volume, number list
ISSN: 0038-1101 (Print)
In this Issue (31 articles)
| 1265 - 1265 |
Special issue devoted to the ESSDERC'07 conference - Foreword Schmitz J, Thewes R |
| 1266 - 1273 |
45 nm/32 nm CMOS - Challenge and perspective Ishimaru K |
| 1274 - 1279 |
High-k-oxide/silicon interfaces characterized by capacitance frequency spectroscopy Raeissi B, Piscator J, Engstrom O, Hall S, Buiu O, Lemme MC, Gottlob HDB, Hurley PK, Cherkaoui K, Osten HJ |
| 1280 - 1284 |
Origin of flat band voltage shift in HfO2 gate dielectric with La2O3 insertion Kakushima K, Okamoto K, Adachi M, Tachi K, Ahmet P, Tsutsui K, Sugii N, Hattori T, Iwai H |
| 1285 - 1290 |
105 nm Gate length pMOSFETs with high-K and metal gate fabricated in a Si process line on 200 mm GeOI wafers Le Royer C, Clavelier L, Tabone C, Romanjek K, Deguet C, Sanchez L, Hartmann JM, Roure MC, Grampeix H, Soliveres S, Le Carval G, Truche R, Pouydebasque A, Vinet M, Deleonibus S |
| 1291 - 1296 |
Multi-gate devices for the 32 nm technology node and beyond Collaert N, De Keersgieter A, Dixit A, Ferain I, Lai LS, Lenoble D, Mercha A, Nackaerts A, Pawlak BJ, Rooyackers R, Schulz T, San KT, Son NJ, Van Dal MJH, Verheyen P, von Arnim K, Witters L, Meyer KD, Biesemans S, Jurczak M |
| 1297 - 1302 |
Impact of the gate stack on the electrical performances of 3D multi-channel MOSFET (MCFET) on SOI Bernard E, Ernst T, Guillaumot B, Vulliet N, Garros X, Maffini-Alvaro V, Coronel P, Skotnicki T, Deleonibus S |
| 1303 - 1311 |
Achieving low-V-T Ni-FUSICMOS via lanthanide incorporation in the gate stack Veloso A, Yu HY, Lauwers A, Chang SZ, Adelmann C, Onsia B, Demand M, Brus S, Vrancken C, Singanamalla R, Lehnen P, Kittl J, Kauerauf T, Vos R, O'Sullivan BJ, Van Elshocht S, Mitsuhashi R, Whittemore G, Yin KM, Niwa M, Hoffmann T, Absil P, Jurczak M, Biesemans S |
| 1312 - 1317 |
Si-nanowire CMOS inverter logic fabricated using gate-all-around (GAA) devices and top-down approach Buddharaju KD, Singh N, Rustagi SC, Teo SHG, Lo GQ, Balasubramanian N, Kwong DL |
| 1318 - 1323 |
A new definition of threshold voltage in Tunnel FETs Boucart K, Ionescu AM |
| 1324 - 1328 |
Examination of the high-frequency capability of carbon nanotube FETs Pulfrey DL, Chen L |
| 1329 - 1335 |
Phonon-scattering effects in CNT-FETs with different dimensions and dielectric materials Grassi R, Poli S, Reggiani S, Gnani E, Gnudi A, Baccarani G |
| 1336 - 1344 |
Punch-through impact ionization MOSFET (PIMOS): From device principle to applications Moselund KE, Bouvet D, Pott V, Meinen C, Kayal M, Ionescu AM |
| 1345 - 1352 |
Single-grain Si thin-film transistors SPICE model, analog and RF circuit applications Baiano A, Danesh M, Saputra N, Ishihara R, Long J, Metselaar W, Beenakker CIM, Karaki N, Hiroshima Y, Inoue S |
| 1353 - 1358 |
Investigation and improvement of DMOS switches under fast electro-thermal cycle stress Smorodin T, Nelle P, Busch J, Wilde J, Glavanovics M, Stecher M |
| 1359 - 1363 |
Aluminum nitride for heatspreading in RF IC's La Spina L, Iborra E, Schellevis H, Clement M, Olivares J, Nanver LK |
| 1364 - 1373 |
Joining microelectronics and microionics: Nerve cells and brain tissue on semiconductor chips Fromherz P |
| 1374 - 1381 |
Finite element analysis and analytical simulations of Suspended Gate-FET for ultra-low power inverters Tsamados D, Chauhan YS, Eggimann C, Akarvardar K, Wong HSP, Ionescu AM |
| 1382 - 1387 |
Anodic Ta2O5 for CMOS compatible low voltage electrowetting-on-dielectric device fabrication Li Y, Parkes W, Haworth LI, Stokes AA, Muir KR, Li P, Collin AJ, Hutcheon NG, Henderson R, Rae B, Walton AJ |
| 1388 - 1393 |
Electrothermal noise analysis in frequency tuning of nanoresonators Jun SC, Son HB, Baik CW, Kim JM, Moon SW, Kim HJ, Huang XMH, Hone J |
| 1394 - 1400 |
Nano-gap micro-electro-mechanical bulk lateral resonators with high quality factors and low motional resistances on thin silicon-on-insulator Badila-Ciressan ND, Mazza M, Grogg D, Ionescu AM |
| 1401 - 1406 |
CMOS image sensors: State-of-the-art Themissen AJP |
| 1407 - 1413 |
Degradation of CMOS image sensors in deep-submicron technology due to gamma-irradiation Rao PR, Wang XY, Theuwissen AJP |
| 1414 - 1423 |
The Monte Carlo approach to transport modeling in deca-nanometer MOSFETs Sangiorgi E, Palestri P, Esseni D, Fiegna C, Selmi L |
| 1424 - 1429 |
On a computationally efficient approach to boron-interstitial clustering Schermer J, Martinez-Limia A, Pichler P, Zechner C, Lerch W, Paul S |
| 1430 - 1436 |
From point defects to dislocation loops: A comprehensive modelling framework for self-interstitial defects in silicon Martin-Bragado I, Avci I, Zographos N, Jaraiz M, Castrillo P |
| 1437 - 1442 |
Microscopic modeling of hole inversion layer mobility in unstrained and uniaxially stressed Si on arbitrarily oriented substrates Pham AT, Jungemann C, Meinerzhagen B |
| 1443 - 1451 |
Status and challenges of phase change memory modeling Lacaita AL, Ielmini D, Mantegazza D |
| 1452 - 1459 |
Integration of CVD silicon nanocrystals in a 32 Mb NOR flash memory Jacob S, De Salvo B, Perniola L, Festes G, Bodnar S, Coppard R, Thiery JF, Pate-Cazal T, Bongiorno C, Lombardo S, Dufourcq J, Jalaguier E, Pedron T, Boulanger F, Deleonibus S |
| 1460 - 1466 |
Long term charge retention dynamics of SONOS cells Arreghini A, Akil N, Driussi F, Esseni D, Selmi L, van Duuren MJ |
| 1467 - 1472 |
Phase-change memory technology with self-aligned mu Trench cell architecture for 90 nm node and beyond Pirovano A, Pellizzer F, Tortorelli I, Rigano A, Harrigan R, Magistretti M, Petruzza P, Varesi E, Redaelli A, Erbetta D, Marangon T, Bedeschi F, Fackenthal R, Atwood G, Bez R |