Solid-State Electronics
Solid-State Electronics, Vol.54, No.9 Entire volume, number list
ISSN: 0038-1101 (Print)
In this Issue (36 articles)
| 809 - 809 |
Selected Papers from the ESSDERC 2009 Conference Foreword Dimoulas A, Tsoukalas D |
| 810 - 817 |
Scaling beyond CMOS: Turing-Heisenberg Rapprochement Zhirnov VV, Cavin RK |
| 818 - 829 |
Ultra-thin chip technology and applications, a new paradigm in silicon technology Burghartz JN, Appel W, Harendt C, Rempp H, Richter H, Zimmermann M |
| 830 - 840 |
Function by defects at the atomic scale - New concepts for non-volatile memories Waser R, Dittmann R, Salinga M, Wuttig M |
| 841 - 848 |
Performance, reliability, radiation effects, and aging issues in microelectronics - From atomic-scale physics to engineering-level modeling Pantelides ST, Tsetseris L, Beck MJ, Rashkeev SN, Hadjisavvas G, Batyrev IG, Tuttle BR, Marinopoulos AG, Zhou XJ, Fleetwood DM, Schrimpf RD |
| 849 - 854 |
Impact of a 10 nm ultra-thin BOX (UTBOX) and ground plane on FDSOI devices for 32 nm node and below Fenouillet-Beranger C, Perreau P, Denorme S, Tosti L, Andrieu F, Weber O, Monfray S, Barnola S, Arvet C, Campidelli Y, Haendler S, Beneyton R, Perrot C, de Buttet C, Gros P, Pham-Nguyen L, Leverd F, Gouraud P, Abbate F, Baron F, Torres A, Laviron C, Pinzelli L, Vetier J, Borowiak C, Margain A, Delprat D, Boedt F, Bourdelle K, Nguyen BY, Faynot O, Skotnicki T |
| 855 - 860 |
Benchmarking SOI and bulk FinFET alternatives for PLANAR CMOS scaling succession Chiarella T, Witters L, Mercha A, Kerner C, Rakowski M, Ortolland C, Ragnarsson LA, Parvais B, De Keersgieter A, Kubicek S, Redolfi A, Vrancken C, Brus S, Lauwers A, Absil P, Biesemans S, Hoffmann T |
| 861 - 869 |
Electrical and diffraction characterization of short and narrow MOSFETs on fully depleted strained silicon-on-insulator (sSOI) Baudot S, Andrieu F, Faynot O, Eymery J |
| 870 - 876 |
Ultra-high aspect-ratio FinFET technology Jovanovic V, Suligoj T, Poljak M, Civale Y, Nanver LK |
| 877 - 882 |
Small-signal analysis of high-performance p- and n-type SOI SB-MOSFETs with dopant segregation Urban C, Emam M, Sandow C, Zhao QT, Fox A, Mantl S, Raskin JP |
| 883 - 889 |
Gate-all-around technology: Taking advantage of ballistic transport? Huguenin JL, Bidal G, Denorme S, Fleury D, Loubet N, Pouydebasque A, Perreau P, Leverd F, Barnola S, Beneyton R, Orlando B, Gouraud P, Salvetat T, Clement L, Monfray S, Ghibaudo G, Boeuf F, Skotnicki T |
| 890 - 896 |
C-V profiling of ultra-shallow junctions using step-like background profiles Popadic M, Milovanovic V, Xu CQ, Sarubbi F, Nanver LK |
| 897 - 902 |
Managing annealing pattern effects in 45 nm low power CMOS technology Morin P, Cacho F, Beneyton R, Dumont B, Colin A, Bono H, Villaret A, Josse E, Bianchini R |
| 903 - 908 |
Formation of silicon ultra shallow junction by non-melt excimer laser treatment Florakis A, Papadimitriou A, Chatzipanagiotis N, Misra N, Grigoropoulos C, Tsoukalas D |
| 909 - 918 |
V-DD scalability of FinFET SRAMs: Robustness of different design options against LER-induced variations Baravelli E, De Marchi L, Speciale N |
| 919 - 924 |
Self-aligned inversion-channel In0.75Ga0.25As metal-oxide-semiconductor field-effect-transistors using UHV-Al2O3/Ga2O3(Gd2O3) and ALD-Al2O3 as gate dielectrics Lin TD, Chiu HC, Chang P, Chang YH, Wu YD, Hong M, Kwo J |
| 925 - 928 |
Electrical characterization of Si nanowire field-effect transistors with semi gate-around structure suitable for integration Sato S, Kamimura H, Arai H, Kakushima K, Ahmet P, Ohmori K, Yamada K, Iwai H |
| 929 - 934 |
A quasi-analytical model for nanowire FETs with arbitrary polygonal cross section De Michielis L, Selmi L, Ionescu AM |
| 935 - 941 |
Asymmetrically strained all-silicon multi-gate n-Tunnel FETs Najmzadeh M, Boucart K, Riess W, Ionescu AM |
| 942 - 949 |
Investigation of the performance of strained-SiGe vertical IMOS-transistors Dinh TV, Kraus R, Jungemann C |
| 950 - 956 |
Theoretical analysis of the vertical LOCOS DMOS transistor with process-induced stress enhancement Reggiani S, Denison M, Gnani E, Gnudi A, Baccarani G, Pendharkar S, Wise R |
| 957 - 964 |
Single-transistor latch-up and large-signal reliability in SOI CMOS RF power transistors Carrara F, Presti CD, Scuderi A, Palmisano G |
| 965 - 971 |
Effective passivation and high-performance metal-oxide-semiconductor devices using ultra-high-vacuum deposited high-kappa dielectrics on Ge without interfacial layers Chu LK, Chu RL, Lin TD, Lee WC, Lin CA, Huang ML, Lee YJ, Kwo J, Hong M |
| 972 - 978 |
HfO2-based gate stacks transport mechanisms and parameter extraction Coignus J, Leroux C, Clerc R, Truche R, Ghibaudo G, Reimbold G, Boulanger F |
| 979 - 984 |
SILC decay in La2O3 gate dielectrics grown on Ge substrates subjected to constant voltage stress Rahman MS, Evangelou EK, Androulidakis II, Dimoulas A, Mavrou G, Galata S |
| 985 - 990 |
A novel self-refreshable capacitorless DRAM cell and its extended applications Wang PF, Liu L, Wu DP, Zang SG, Liu W, Gong Y, Zhang DW, Zhang SL |
| 991 - 996 |
Estimation of amorphous fraction in multilevel phase-change memory cells Papandreou N, Pantazi A, Sebastian A, Eleftheriou E, Breitwisch M, Lam C, Pozidis H |
| 997 - 1002 |
Modeling of gate-all-around charge trapping SONOS memory cells Gnani E, Reggiani S, Gnudi A, Baccarani G, Fu J, Singh N, Lo GQ, Kwong DL |
| 1003 - 1009 |
Double-gate pentacene thin-film transistor with improved control in sub-threshold region Tsamados D, Cvetkovic NV, Sidler K, Bhandari J, Savu V, Brugger J, Ionescu AM |
| 1010 - 1014 |
Epitaxial graphene field-effect transistors on silicon substrates Kang HC, Karasawa H, Miyamoto Y, Handa H, Suemitsu T, Suemitsu M, Otsuji T |
| 1015 - 1021 |
Simple and efficient modeling of the E-k relationship and low-field mobility in Graphene Nano-Ribbons Bresciani M, Palestri P, Esseni D, Selmi L |
| 1022 - 1026 |
Magneto-modulation of gate leakage current in 65 nm nMOS transistors: Experimental, modeling, and simulation results Gutierrez EA, Molina J, Garcia P, Martinez J, Guarin F |
| 1027 - 1032 |
On-chip Extraordinary Hall-effect sensors for characterization of nanomagnetic logic devices Becherer M, Kiermaier J, Breitkreutz S, Csaba G, Ju X, Rezgani J, Kiessling T, Yilmaz C, Osswald P, Lugli P, Schmitt-Landsiedel D |
| 1033 - 1040 |
Tunable band-stop filter based on single RF MEMS capacitive shunt switch with meander arm inductance Fernandez-Bolanos M, Dehollain C, Nicole P, Ionescu AM |
| 1041 - 1046 |
Solidly mounted BAW resonators with layer-transferred AlN using sacrificial Si surfaces Allah MA, Thalhammer R, Kaitila J, Herzog T, Weber W, Schmitt-Landsiedel D |
| 1047 - 1050 |
Electron magnetoresistance mobility in silicon-on-insulator layers using Kelvin's technique Antoszewski J, Dell JM, Faraone L, Bresson N, Cristoloveanu S |