In order for SiC power MOSFETs to provide high breakdown voltage, punch-through that occurs in the P-well must be prevented. For that purpose, it is necessary to fabricate a deep P-well, but that is hard to accomplish especially in SiC. This is the first detailed analysis of a shallow P-well profile of 4H-SiC power MOSFETs without punch-through. In the shallow P-well the carrier concentration at a depth of 0.3-0.8 mum was high and the surface concentration was low enough for channel formation. The optimized P-well profile was obtained by conducting a 2-dimensional numerical simulation with Dessis (ISE). When the peak concentration of the P-well was over 3e17cm(-3), the ideal avalanche breakdown was obtained even though the P-well depth was only 0.8 mum. We also analyzed the electric field distributions of this device structure. The electric field of the gate oxide on the HET area of this device was below 3 MV/cm at a drain voltage of 1kV when the P-well interval (JFET area length) was 2 mum. These results are practical and the device can be fabricated by normal ion-implantation techniques.