화학공학소재연구정보센터
Solid-State Electronics, Vol.72, 78-81, 2012
Modeling and extraction technique for parasitic resistances in MOSFETs Combining DC I-V and low frequency C-V measurement
Accurate extraction of parasitic gate (R-G), source (R-S), drain (R-D), and substrate (R-sub) resistances in MOSFETs is important in the modeling and characterization for DC and RF applications. Combining DC current-voltage and low-frequency capacitance-voltage characteristics with an equivalent circuit, we report a simple technique for a complete and separate extraction of parasitic resistances (R-G, R-S, R-D, and R-sub) in individual MOSFETs without employing multiple devices or complicated S-parameter characterization with various device combinations. Intrinsic spreading component is also separated from the contact-related extrinsic component in R-S and R-D. (c) 2012 Elsevier Ltd. All rights reserved.