In this paper, a scheme for how to utilize VFTLP (very fast transmission line pulse) data to design an input buffer circuit for CDM (charged-device model) ESD protection is reported. The impedance of the ESD device under VFTLP stress is nearly 120 Omega at the beginning of turn-on transient, and decreases with time toward 10 Omega prior to the voltage falling below 0 V. In this work, the fact that the dynamic-characteristic impedance of the ESD device under VFTLP testing is independent of the stress current is found. Since both VFTLP zapping and the CDM are nanosecond events, the dynamic-characteristic impedance of the ESD device can be used to evaluate the CDM threshold voltage of the input buffer based on the equivalent and simplified RLC circuit. (C) 2014 Elsevier Ltd. All rights reserved.