A full capacitance model for Amorphous Oxide Semiconductor Thin Film Transistors (AOSTFTs), considering the effect of the drain contact overlap in bottom gate passivated structures is presented. It is shown that this drain overlap, on top of the passivation layer, serves as a second gate with an applied voltage equal to V-DS. When V-DS > V-T the semiconductor-passivation (S-P) interface will be in accumulation and the behavior of the different capacitance is affected. An expression to represent this effect is included in the present model. The overlap capacitance between gate and drain/source, as well as the effect of reducing the channel capacitance as the drain is increased, are also considered by the model. The calculated capacitance is a function of the threshold voltage, (V-T), the mobility and saturation parameters (gamma(a), alpha(s)), and the sharpness of the knee region m, which are extracted using the Unified Model and Extraction Method (UMEM) for AOSTFTs. Results are compared with simulated and experimental data.