A new process flow is proposed (C.J.R.P. Augusto, U.S. Provisional Patent Appl. No, 60/008703, 1995) for the fabrication of silicon-based MOD-MOSFETs, with or without SiGe relaxed buffer layers. In this process flow, a single, blanket, epitaxial step is used to make all regions of the complementary devices. No ion implantation is required, thereby lifting thermal budget constraints on the metastability of the epitaxial films. Because this process flow can be used to produce recessed-gate MOSFETs, this architecture can be scaled to the 0.1 mu m region, preserving very low leakage currents, independent of the drain bias. Moreover, the number of processing steps needed to fabricate these devices is greatly reduced.