This paper describes the use of narrow collector layers in planar LOGOS isolated Si and SiGe bipolar transistors. The transistors have been fabricated using either a single or double epi process in order to compare the doping control in the collector layer. In contrast with the conventional double epi process, in the single epi process, the collector, base and emitter Layers were all deposited in one single step after the high thermal budget LOGOS process. We show that the single epi process minimises dopant outdiffusion from the n(+) buried subcollector, thus offering the potential of submicron low doped collector and the benefit of reduced epitaxy cost. Attention is drawn to the leakage current in the base-collector junction when intersecting the poly-Si/Si deposited at the oxide window edge.