The fabrication of silicon layers doped in situ with phosphor using CVD technique is still poorly controlled by the microelectronics industry. Significant thickness heterogeneities are noticeable on circuit and load, which greatly limits the process utilization. An experimental study of this deposition was carried out. The influence of many parameters (temperature, pressure, feed composition) was studied in terms of deposition thickness and uniformity as well as crystalline structure and resistivity. The advantages and involved mechanisms are presented.