The undesired effects of photoresist patterning and ion implantation toward achieving optimum yields for flash electrically erasable-programmable read-only memory ((EPROM)-P-2) devices are investigated. The conventional utilization of a blanket resist with small windows open at the source area of each cell for the conduction of an additional dopant implantation saw a much lower yield similar to 45% for the completed devices when compared to those using isolated resist cell windows for the same implant step similar to 70%. In addition, the former also displays poorer data retention capability owing to degraded tunneling dielectric quality, i.e., the device data retention loss for blanket resist patterning scheme is similar to 30% lower than what is registered in the improved scheme. The substantial improvement in both device yield and data retention capability for the latter arises from the reduction in the magnitude of surging current, which is made up by the dopant ionized charges, down the substrate via the open windows.