화학공학소재연구정보센터
Electrochemical and Solid State Letters, Vol.3, No.7, 343-345, 2000
Impact of cooling rate in annealing for iron gettering in p/p(+) silicon device wafers
We investigated the leakage current characteristics of n(+)-p junction on intentionally Fe contaminated p/p(+) device wafers. There are two initial Fe concentration levels. One is at 5 x 10(11) cm(-2) and the other is at 5 x 10(12) cm(-2). Two types of n(+)-p junction, with LOCOS and gate structure as periphery, were used to investigate the effect of device structures on Fe gettering. The annealing for Fe gettering was done at 900 degrees C for 15 min with two different cooling conditions. The leakage current characteristic does not depend on the initial Fe contamination levels but on the cooling rate during gettering. The "slow" cooling is more effective for reducing the leakage current than the "fast" one, because most of the Fe moves to the p(+) substrate. But during the fast cooling experiments, the Fe ions are accumulated around the device structures. Furthermore, the observed leakage characteristics show that the LOCOS structures act as the strongest gettering sites as compared to the n-type diffusion layers and the gate structures.