Although considered as a basic building lock for electronic circuits, the conventional Darlington pair suffers from weaknesses at high frequencies. To overcome this problem several modifications of this pair have been suggested. A quantitative assessment of the effects of newly introduced parameters on the performance efficiency of one such modified Darlington pair design has been performed. Pspice simulation has been used to make this assessment which throws significant light on the need of trade-off between the high cut-off frequency F-H and the voltage gain A(V) to achieve the best possible solution. (C) 2002 Elsevier Science Ltd. All rights reserved.