We present simulations of a recently published multi-barrier phase-state low electron device memory cell. For the proper consideration of tunneling through the insulating barriers we implemented a one-dimensional Schrodinger solver based on the transfer-matrix formalism into the device simulator MINIMOS-NT. We investigate the effect of barrier size and position on the I-on/I-off ratio of the memory cell. We find that the position and thickness of the central shutter barrier can be used for device tuning. For high I-on/I-off ratios the central shutter barrier (CSB) should be placed Dear the upper contact. Furthermore, a reduction in the stack width leads to increasing I-on/I-off ratios. Although the use of the transfer-matrix method in a device simulator requires a number of assumptions, it turns out to be a viable tool for deepening the understanding of tunneling effects in devices where other tunneling models fail. (C) 2002 Elsevier Science Ltd. All rights reserved.