Operation mechanisms of devices with electrically floating regions have been analyzed by device simulations. An insulator has been modeled as a wide-gap semiconductor and the device simulation has been carried out in the whole region including insulator and floating regions. By using this approach, we have evaluated electrical properties of the capacitances used to represent such devices; i.e., the capacitance of interconnect structures with metal-fill and the drain capacitance of an advanced SOI-MOSFET with an electrically floating interlayer. When one-fourth of an insulating area between parallel interconnect-lines is occupied by a squared fill, the capacitance between the lines was found to increase by three-fourths, over the value for a parallel plate capacitance without dummy fills. Also, the drain capacitance of an advanced SOI-MOSFET structure, i.e., a Si/oxide/poly-Si/oxide/Si-substrate, was analyzed. When the doping concentration of the electrically floating poly-Si interlayer is not so high, the interlayer is partially depleted and a depletion capacitor is formed. The floating potential varies non-linearly with the applied bias and is smaller than the bias. The total capacitance of a multi-oxide-layered SOI-MOSFET structure is much lower than the MOS capacitance estimated from the oxide thickness. Floating elements have great advantages in terms of decreasing capacitance values. (C) 2004 Elsevier Ltd. All rights reserved.