Ultra-low off current (I-off < 1 pA/mu m) "silicon on thin buried oxide (SOTB)" CMOSFETs were developed using 65-nm technology. The off current of SOTB CMOSFETs was studied and gate-induced drain leakage (GIDL) was adequately reduced by controlling the gate-overlap length. A back-gate bias in a SOTB scheme was demonstrated, and the inverter delay was compared with conventional low-standby-power bulk CMOSFETs. We show small variation in SOTB devices and estimate the standby leakage of a 1-M bit SRAM. The half threshold voltage standard deviation (sigma V-th) of SOTB devices corresponds to a reduction in the standby leakage current of less than half. The ultra-low off current with a small variation also further reduces the standby leakage. (C) 2009 Elsevier Ltd. All rights reserved.