검색결과 : 7건
| No. | Article |
|---|---|
| 1 |
Hard breakdown mechanisms of compensated p-type and n-type single-crystalline silicon solar cells Dubois S, Veirman J, Enjalbert N, Scheiblin P Solid-State Electronics, 76, 36, 2012 |
| 2 |
In-depth physical investigation of GeOI pMOSFET by TCAD calibrated simulation Grandchamp B, Jaud MA, Scheiblin P, Romanjek K, Hutin L, Le Royer C, Vinet M Solid-State Electronics, 57(1), 67, 2011 |
| 3 |
Dual strained channel CMOS in FDSOI architecture: New insights on the device performance Le Royer C, Casse M, Cooper D, Andrieu F, Weber O, Brevard L, Perreau P, Damlencourt JF, Baudot S, Previtali B, Tabone C, Allain F, Scheiblin P, Rauer C, Figuet C, Aulnette C, Daval N, Nguyen BY, Bourdelle KK, Gyani J, Valenza M Solid-State Electronics, 65-66, 9, 2011 |
| 4 |
Amorphization, recrystallization and end of range defects in germanium Claverie A, Koffel S, Cherkashin N, Benassayag G, Scheiblin P Thin Solid Films, 518(9), 2307, 2010 |
| 5 |
Honeycomb voids due to ion implantation in germanium Kaiser RJ, Koffel S, Pichler P, Bauer AJ, Amon B, Claverie A, Benassayag G, Scheiblin P, Frey L, Ryssel H Thin Solid Films, 518(9), 2323, 2010 |
| 6 |
High performance 70 nm gate length germanium-on-insulator pMOSFET with high-k/metal gate Romanjek K, Hutin L, Le Royer C, Pouydebasque A, Jaud MA, Tabone C, Augendre E, Sanchez L, Hartmann JM, Grampeix H, Mazzocchi V, Soliveres S, Truche R, Clavelier L, Scheiblin P, Garros X, Reimbold G, Vinet M, Boulanger F, Deleonibus S Solid-State Electronics, 53(7), 723, 2009 |
| 7 |
FDSOI devices with thin BOX and ground plane integration for 32 nm node and below Fenouillet-Beranger C, Denorme S, Perreau P, Buj C, Faynot O, Andrieu F, Tosti L, Barnola S, Salvetat T, Garros X, Casse M, Allain F, Loubet N, Pham-Nguyen L, Deloffre E, Gros-Jean M, Beneyton R, Laviron C, Marin M, Leyris C, Haendler S, Leverd F, Gouraud P, Scheiblin P, Clement L, Pantel R, Deleonibus S, Skotnicki T Solid-State Electronics, 53(7), 730, 2009 |