검색결과 : 8건
No. | Article |
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1 |
Understanding and optimizing the floating body retention in FDSOI UTBOX Aoulaiche M, Simoen E, Caillat C, Witters L, Bourdelle KK, Nguyen BY, Martino J, Claeys C, Fazan P, Jurczak M Solid-State Electronics, 117, 123, 2016 |
2 |
Self-aligned double patterning process for subtractive Ge fin fabrication at 45-nm pitch Milenin AP, Witters L, Barla K, Thean A Thin Solid Films, 602, 64, 2016 |
3 |
Integration aspects of strained Ge pFETs Witters L, Eneman G, Mitard J, Vincent B, Hikavyy A, Milenin AP, Mertens S, Thean A, Collaert N Solid-State Electronics, 98, 7, 2014 |
4 |
Growth of high Ge content SiGe on (110) oriented Si wafers Hikavyy A, Vanherle W, Vincent B, Dekoster J, Bender H, Moussa A, Witters L, Hoffman T, Loo R Thin Solid Films, 520(8), 3179, 2012 |
5 |
The implant-free quantum well field-effect transistor: Harnessing the power of heterostructures Hellings G, Hikavyy A, Mitard J, Witters L, Benbakhti B, Alian A, Waldron N, Bender H, Eneman G, Krom R, Schulze A, Vandervorst W, Loo R, Heyns M, Meuris M, Hoffmann T, De Meyer K Thin Solid Films, 520(8), 3326, 2012 |
6 |
Benchmarking SOI and bulk FinFET alternatives for PLANAR CMOS scaling succession Chiarella T, Witters L, Mercha A, Kerner C, Rakowski M, Ortolland C, Ragnarsson LA, Parvais B, De Keersgieter A, Kubicek S, Redolfi A, Vrancken C, Brus S, Lauwers A, Absil P, Biesemans S, Hoffmann T Solid-State Electronics, 54(9), 855, 2010 |
7 |
Performance improvement in narrow MuGFETs by gate work function and source/drain implant engineering Ferain I, Duffy R, Collaert N, van Dal MJH, Pawlak BJ, O'Sullivan B, Witters L, Rooyackers R, Conard T, Popovici M, van Elshocht S, Kaiser M, Weemaes RGR, Swerts J, Jurczak M, Lander RJP, De Meyer K Solid-State Electronics, 53(7), 760, 2009 |
8 |
Multi-gate devices for the 32 nm technology node and beyond Collaert N, De Keersgieter A, Dixit A, Ferain I, Lai LS, Lenoble D, Mercha A, Nackaerts A, Pawlak BJ, Rooyackers R, Schulz T, San KT, Son NJ, Van Dal MJH, Verheyen P, von Arnim K, Witters L, Meyer KD, Biesemans S, Jurczak M Solid-State Electronics, 52(9), 1291, 2008 |