Solid-State Electronics

Solid-State Electronics, Vol.52, No.12 Entire volume, number list

ISSN: 0038-1101 (Print)

In this Issue (18 articles)

1839 - 1839	SELECTED PAPERS FROM THE EUROSOI'08 CONFERENCE Foreword Lederer D, Colinge JP
1840 - 1844	Germanium on sapphire by wafer bonding Baine PT, Gamble HS, Armstrong BM, McNeill DW, Mitchell SJN, Low YH, Rainey PV
1845 - 1848	Evaluation of super-critical thickness strained-Si on insulator (sc-SSOI) substrate Ogura A, Yoshida T, Kosemura D, Kakemura Y, Takei M, Saito H, Shimura T, Koganesawa T, Hirosawa I
1849 - 1853	Fabrication and characterisation of high resistivity SOI substrates for monolithic high energy physics detectors Ruddell FH, Suder SL, Bain MF, Montgomery JH, Armstrong BM, Gamble HS, Denvir D, Casse G, Bowcock T, Allport PP, Marczewski J, Kucharski K, Tomaszewski D, Niemiec H, Kucewicz W
1854 - 1860	Modeling the equivalent oxide thickness of Surrounding Gate SOI devices with high-kappa insulators Tienda-Luna IM, Ruiz FJG, Donetti L, Godoy A, Gamiz F
1861 - 1866	Electron subband structure and controlled valley splitting in silicon thin-body SOI FETs: Two-band k.p theory and beyond Sverdlov V, Selberherr S
1867 - 1871	Compact charge and capacitance modeling of undoped ultra-thin body (UTB) SOI MOSFETs Moldovan O, Chaves FA, Jimenez D, Iniguez B
1872 - 1876	Sensitivity of trigate MOSFETs to random dopant induced threshold voltage fluctuations Yan R, Lynch D, Cayron T, Lederer D, Afzalian A, Lee CW, Dehdashti N, Colinge JP
1877 - 1883	Threshold voltages of SOI MuGFETs de Andrade MGC, Martino JA
1884 - 1888	Analysis of STI-induced mechanical stress-related Kink effect of 40 nm PD SOI NMOS devices biased in saturation region Lin IS, Su VC, Kuo JB, Chen D, Yeh CS, Tsai CT, Ma M
1889 - 1894	Impact of strain and source/drain engineering on the low frequency noise behaviour in n-channel tri-gate FinFETs Guo W, Cretu B, Routoure JM, Carin R, Simoen E, Mercha A, Collaert N, Put S, Claeys C
1895 - 1903	How crucial is back gate misalignment/oversize in double gate MOSFETs for ultra-low-voltage analog/rf applications? Kranti A, Armstrong GA
1904 - 1909	Analog performance of standard and strained triple-gate silicon-on-insulator nFinFETs Pavanello MA, Martino JA, Simoen E, Rooyackers R, Collaert N, Claeys C
1910 - 1914	Substrate bias and operating temperature effects on the performance of Schottky-barrier SOI nMOSFETs Ka DH, Shin JW, Cho WJ, Park JT
1915 - 1923	Temperature behavior of spiral inductors on high resistivity substrate in SOI CMOS technology El Kaamouchi M, Delatte P, Moussa MS, Raskin JP, Vanhoenacker-Janvier D
1924 - 1932	High-temperature DC and RF behaviors of partially-depleted SOI MOSFET transistors Emam M, Tinoco JC, Vanhoenacker-Janvier D, Raskin JP
1933 - 1938	Advantages of graded-channel SOI nMOSFETs for application as source-follower analog buffer de Souza M, Flandre D, Pavanello MA
1939 - 1945	Building ultra-low-power high-temperature digital circuits in standard high-performance SOI technology Bol D, De Vos J, Ambroise R, Flandre D, Legat JD