검색결과 : 38건
| No. | Article |
|---|---|
| 1 |
Fabrication of Silicon on Diamond (SOD) substrates by either the Bonded and Etched-back SOI (BESOI) or the Smart-Cut (TM) technology Widiez J, Rabarot M, Saada S, Mazellier JP, Dechamp J, Delaye V, Roussin JC, Andrieu F, Faynot O, Deleonibus S, Bergonzo P, Clavelier L Solid-State Electronics, 54(2), 158, 2010 |
| 2 |
High performance 70 nm gate length germanium-on-insulator pMOSFET with high-k/metal gate Romanjek K, Hutin L, Le Royer C, Pouydebasque A, Jaud MA, Tabone C, Augendre E, Sanchez L, Hartmann JM, Grampeix H, Mazzocchi V, Soliveres S, Truche R, Clavelier L, Scheiblin P, Garros X, Reimbold G, Vinet M, Boulanger F, Deleonibus S Solid-State Electronics, 53(7), 723, 2009 |
| 3 |
FDSOI devices with thin BOX and ground plane integration for 32 nm node and below Fenouillet-Beranger C, Denorme S, Perreau P, Buj C, Faynot O, Andrieu F, Tosti L, Barnola S, Salvetat T, Garros X, Casse M, Allain F, Loubet N, Pham-Nguyen L, Deloffre E, Gros-Jean M, Beneyton R, Laviron C, Marin M, Leyris C, Haendler S, Leverd F, Gouraud P, Scheiblin P, Clement L, Pantel R, Deleonibus S, Skotnicki T Solid-State Electronics, 53(7), 730, 2009 |
| 4 |
New floating-body effect in partially depleted SOI pMOSFET due to direct-tunneling current in the partial n plus poly gate Guegan G, Gwoziecki R, Touret P, Raynaud C, Pretet J, Gonnard O, Gouget G, Deleonibus S Solid-State Electronics, 53(7), 741, 2009 |
| 5 |
Method for 3D electrical parameters dissociation and extraction in multichannel MOSFET (MCFET) Dupre C, Ernst T, Bernard E, Guillaumot B, Vulliet N, Coronel P, Skotnicki T, Cristoloveanu S, Ghibaudo G, Faynot O, Deleonibus S Solid-State Electronics, 53(7), 746, 2009 |
| 6 |
Impact of a HTO/Al2O3 bi-layer blocking oxide in nitride-trap non-volatile memories Bocquet M, Molas G, Perniola L, Garros X, Buckley J, Gely M, Colonna JP, Grampeix H, Martin F, Vidal V, Toffoli A, Deleonibus S, Ghibaudo G, Pananakakis G, De Salvo B Solid-State Electronics, 53(7), 786, 2009 |
| 7 |
Monte-Carlo simulation of MOSFETs with band offsets in the source and drain Braccioli M, Palestri P, Mouis M, Poiroux T, Vinet M, Le Carval G, Fiegna C, Sangiorgi E, Deleonibus S Solid-State Electronics, 52(4), 506, 2008 |
| 8 |
3D nanowire gate-all-around transistors: Specific integration and electrical features Dupre C, Ernst T, Maffim-Alvaro V, Delaye V, Hartmann JM, Borel S, Vizoz C, Faynot O, Ghibaudo G, Deleonibus S Solid-State Electronics, 52(4), 519, 2008 |
| 9 |
105 nm Gate length pMOSFETs with high-K and metal gate fabricated in a Si process line on 200 mm GeOI wafers Le Royer C, Clavelier L, Tabone C, Romanjek K, Deguet C, Sanchez L, Hartmann JM, Roure MC, Grampeix H, Soliveres S, Le Carval G, Truche R, Pouydebasque A, Vinet M, Deleonibus S Solid-State Electronics, 52(9), 1285, 2008 |
| 10 |
Impact of the gate stack on the electrical performances of 3D multi-channel MOSFET (MCFET) on SOI Bernard E, Ernst T, Guillaumot B, Vulliet N, Garros X, Maffini-Alvaro V, Coronel P, Skotnicki T, Deleonibus S Solid-State Electronics, 52(9), 1297, 2008 |