Solid-State Electronics

Solid-State Electronics, Vol.90 Entire volume, number list

ISSN: 0038-1101 (Print)

In this Issue (26 articles)

1 - 1	Foreword Bawedin M
2 - 11	A systematic study of the sharp-switching Z(2)-FET device: From mechanism to modeling and compact memory applications Wan J, Le Royer C, Zaslavsky A, Cristoloveanu S
12 - 17	A physically-based threshold voltage definition, extraction and analytical model for junctionless nanowire transistors Trevisoli RD, Doria RT, de Souza M, Pavanello MA
18 - 22	An analytical mobility model for square Gate-All-Around MOSFETs Tienda-Luna IM, Roldan JB, Ruiz FG, Blanque CM, Gamiz F
23 - 27	On the extension of ET-FDSOI roadmap for 22 nm node and beyond Sampedro C, Gamiz F, Godoy A
28 - 33	Impact ionization induced dynamic floating body effect in junctionless transistors Yu R, Nazarov AN, Lysenko VS, Das S, Ferain I, Razavi P, Shayesteh M, Kranti A, Duffy R, Colinge JP
34 - 38	Subband splitting and surface roughness induced spin relaxation in (001) silicon SOI MOSFETs Osintsev D, Baumgartner O, Stanojevic Z, Sverdlov V, Selberherr S
39 - 43	Transistors on hybrid UTBB/Bulk substrates fabricated by local internal BOX dissolution Nguyen P, Andrieu F, Casse M, Tabone C, Perreau P, Lafond D, Dansas H, Tosti L, Veytizou C, Landru D, Kononchuk O, Guiot E, Nguyen BY, Faynot O, Poiroux T
44 - 50	Bandstructure and mobility variations in p-type silicon nanowires under electrostatic gate field Neophytou N, Baumgartner O, Stanojevic Z, Kosina H
51 - 55	Comprehensive study of the statistical variability in a 22 nm fully depleted ultra-thin-body SOI MOSFET Zain ASM, Markov S, Cheng BJ, Asenov A
56 - 64	UTBB SOI MOSFETs analog figures of merit: Effects of ground plane and asymmetric double-gate regime Arshad MKM, Makovejev S, Olsen S, Andrieu F, Raskin JP, Flandre D, Kilchytska V
65 - 72	Characterization of heavily doped SOI wafers under pseudo-MOSFET configuration Liu FY, Diab A, Ionica I, Akarvardar K, Hobbs C, Ouisse T, Mescot X, Cristoloveanu S
73 - 78	Radio-frequency and low noise characteristics of SOI technology on plastic for flexible electronics des Etangs-Levallois AL, Lesecq M, Danneville F, Tagro Y, Lepilliet S, Hoel V, Troadec D, Gloria D, Raynaud C, Dubois E
79 - 85	Normally-off GaN MOSFETs on insulating substrate Kim DS, Im KS, Kim KW, Kang HS, Kim DK, Chang SJ, Bae Y, Hahm SH, Cristoloveanu S, Lee JH
86 - 93	Revisited parameter extraction methodology for electrical characterization of junctionless transistors Jeon DY, Park SJ, Mouis M, Berthome M, Barraud S, Kim GT, Ghibaudo G
94 - 98	Characterization and optimization of partially depleted SOI MOSFETs for high power RF switch applications Im D, Lee K
99 - 106	Operation and stability analysis of bipolar OxRRAM-based Non-Volatile 8T2R SRAM as solution for information back-up Hraziia, Makosiej A, Palma G, Portal JM, Bocquet M, Thomas O, Clermidy F, Reyboz M, Onkaraiah S, Muller C, Deleruyelle D, Vladimirescu A, Amara A, Anghel C
107 - 115	Threshold voltage, and 2D potential modeling within short-channel junctionless DG MOSFETs in subthreshold region Holtij T, Schwarz M, Kloes A, Iniguez B
116 - 120	Modeling of low frequency noise in FD SOI MOSFETs El Husseini J, Martinez F, Valenza M, Ritzenthaler R, Lime F, Iniguez B, Faynot O, Le Royer C, Andrieu F
121 - 126	Low-frequency noise of n-type triple gate FinFETs fabricated on standard and 45 degrees rotated substrates Doria RT, Martino JA, Simoen E, Claeys C, Pavanello MA
127 - 133	A new characterization technique for SOI wafers: Split C(V) in pseudo-MOSFET configuration Diab A, Fernandez C, Ohata A, Rodriguez N, Ionica I, Bae Y, Van den Daele W, Allibert F, Gamiz F, Ghibaudo G, Mazure C, Cristoloveanu S
134 - 142	Mobility behavior and models for fully depleted nanocrystalline ZnO thin film transistors Chang SJ, Cheralathan M, Bawedin M, Iniguez B, Bayraktaroglu B, Lee JH, Lee JH, Cristoloveanu S
143 - 148	Study of substrate orientations impact on Ultra Thin Buried Oxide (UTBOX) FDSOI High-K Metal gate technology performances Ben Akkez I, Fenouillet-Beranger C, Cros A, Perreau P, Haendler S, Weber O, Andrieu F, Pellissier-Tanon D, Abbate F, Richard C, Beneyton R, Gouraud P, Margain A, Borowiak C, Gourvest E, Bourdelle KK, Nguyen BY, Poiroux T, Skotnicki T, Faynot O, Balestra F, Ghibaudo G, Boeuf F
149 - 154	Optimizing the front and back biases for the best sense margin and retention time in UTBOX FBRAM Almeida LM, Sasaki KRA, Caillat C, Aoulaiche M, Collaert N, Jurczak M, Simoen E, Claeys C, Martino JA
155 - 159	Stress engineering and proton radiation influence on off-state leakage current in triple-gate SOI devices Agopian PGD, Bordallo CCM, Simoen E, Claeys C, Martino JA
160 - 165	DC and low frequency noise performances of SOI p-FinFETs at very low temperature Achour H, Talmat R, Cretu B, Routoure JM, Benfdila A, Carin R, Collaert N, Simoen E, Mercha A, Claey C