Solid-State Electronics

Solid-State Electronics, Vol.54, No.2 Entire volume, number list

ISSN: 0038-1101 (Print)

In this Issue (21 articles)

85 - 85	SELECTED FULL-LENGTH EXTENDED PAPERS FROM THE EUROSOI 2009 CONFERENCE Foreword Engstrom O
86 - 89	SOI versus bulk-silicon nanoscale FinFETs Fossum JG, Zhou ZM, Mathew L, Nguyen BY
90 - 96	Thin-film devices for low power applications Monfra S, Fenouillet-Beranger C, Bidal G, Boeuf F, Denorme S, Huguenin JL, Samson MP, Loubet N, Hartmann JM, Campidelli Y, Destefanis V, Arvet C, Benotmane K, Clement L, Faynot O, Skotnicki T
97 - 103	Performance estimation of junctionless multigate transistors Lee CW, Ferain I, Afzalian A, Yan R, Akhavan ND, Razavi P, Colinge JP
104 - 114	Dynamic body potential variation in FD SOI MOSFETs operated in deep non-equilibrium regime: Model and applications Bawedin M, Cristoloveanu S, Flandre D, Udrea F
115 - 122	Suppression of gate-induced drain leakage by optimization of junction profiles in 22 nm and 32 nm SOI nFETs Schenk A
123 - 130	Mobility enhancement by CESL strain in short-channel ultrathin SOI MOSFETs Pham-Nguyen L, Fenouillet-Beranger C, Ghibaudo G, Skotnicki T, Cristoloveanu S
131 - 136	Multi-Subband Monte Carlo study of device orientation effects in ultra-short channel DGSOI Sampedro C, Gamiz F, Godoy A, Valin R, Garcia-Loureiro A, Ruiz FG
137 - 142	Electron subband structure in strained silicon UTB films from the Hensel-Hasegawa-Nakayama model - Part 1 analytical consideration and strain-induced valley splitting Windbacher T, Sverdlov V, Baumgartner O, Selberherr S
143 - 148	Electron subband structure in strained silicon UTB films from the Hensel-Hasegawa-Nakayama model - Part 2 efficient self-consistent numerical solution of the k . p schrodinger equation Baumgartner O, Karner M, Sverdlov V, Kosina H
149 - 152	Physical modeling of millimetre wave signal reflection from forward biased PIN diodes Jackson RP, Mitchell SJN, Fusco V
153 - 157	Oxygen out-diffusion from buried layers in SOI and SiC-SOI substrates Li LG, Vallin O, Lu J, Smith U, Norstrom H, Olsson J
158 - 163	Fabrication of Silicon on Diamond (SOD) substrates by either the Bonded and Etched-back SOI (BESOI) or the Smart-Cut (TM) technology Widiez J, Rabarot M, Saada S, Mazellier JP, Dechamp J, Delaye V, Roussin JC, Andrieu F, Faynot O, Deleonibus S, Bergonzo P, Clavelier L
164 - 170	Experimental study of transconductance and mobility behaviors in ultra-thin SOI MOSFETs with standard and thin buried oxides Rudenko T, Kilchytska V, Burignat S, Raskin JP, Andrieu F, Faynot O, Le Tiec Y, Landry K, Nazarov A, Lysenko VS, Flandre D
171 - 177	Large-signal analysis of substrate effects in RF-power SOI-LDMOS transistors Vestling L, Bengtsson O, Mum KH, Olsson J
178 - 184	Effect of rotation, gate-dielectric and SEG on the noise behavior of advanced SOI MuGFETs Put S, Mehta H, Collaert N, Van Uffelen M, Leroux P, Claeys C, Lukyanchikova N, Simoen E
185 - 190	Systematic study of Schottky barrier MOSFETs with dopant segregation on thin-body SOI Urban C, Sandow C, Zhao QT, Knoch J, Lenk S, Mantl S
191 - 195	Hole transport in DGSOI devices: Orientation and silicon thickness effects Donetti L, Gamiz F, Rodriguez N, Jimenez-Molinos F, Roldan JB
196 - 204	Effect of high-energy neutrons on MuGFETs Kilchytska V, Alvarado J, Collaert N, Rooyakers R, Militaru O, Berger G, Flandre D
205 - 212	Low-temperature characterization and modeling of advanced GeOI pMOSFETs: Mobility mechanisms and origin of the parasitic conduction Van Den Daele W, Augendre E, Le Royer C, Damlencourt JF, Grandchamp B, Cristoloveanu S
213 - 219	Substrate impact on threshold voltage and subthreshold slope of sub-32 nm ultra thin SOI MOSFETs with thin buried oxide and undoped channel Burignat S, Flandre D, Arshad MKM, Kilchytska V, Andrieu F, Faynot O, Raskin JP