Solid-State Electronics
Solid-State Electronics, Vol.53, No.7 Entire volume, number list
ISSN: 0038-1101 (Print)
In this Issue (23 articles)
| 675 - 675 |
PAPERS SELECTED FROM THE 38TH EUROPEAN SOLID-STATE DEVICE RESEARCH CONFERENCE - ESSDERC'08 Foreword Ashburn P, Hall S |
| 676 - 683 |
Overview and future challenges of floating body RAM (FBRAM) technology for 32 nm technology node and beyond Hamamoto T, Ohsawa T |
| 684 - 693 |
Micropower energy harvesting Vullers RJM, van Schaijk R, Doms I, Van Hoof C, Mertens R |
| 694 - 700 |
Comprehensive study of S/D engineering for 32 nm node CMOS in direct silicon bonded (DSB) technology Yasutake N, Nomachi A, Itokawa H, Morooka T, Zhang L, Fukushima T, Harakawa H, Mizushima I, Azuma A, Toyosihma Y |
| 701 - 705 |
Dual metal gate FinFET integration by Ta/Mo diffusion technology for V-t reduction and multi-V-t CMOS application Matsukawa T, Endo K, Liu YX, O'uchi S, Ishikawa Y, Yamauchi H, Tsukada J, Ishii K, Sakamoto K, Suzuki E, Masahara M |
| 706 - 711 |
Drain current improvements in uniaxially strained p-MOSFETs: A Multi-Subband Monte Carlo study Conzatti F, De Michielis M, Esseni D, Palestri P |
| 712 - 716 |
A study on aggressive proximity of embedded SiGe with comprehensive source drain extension engineering for 32 nm node high-performance pMOSFET technology Okamoto H, Yasutake N, Kusunoki N, Adachi K, Itokawa H, Miyano K, Ishida T, Hokazono A, Kawanaka S, Mizushima I, Azuma A, Toyoshima Y |
| 717 - 722 |
Silicon on thin BOX (SOTB) CMOS for ultralow standby power with forward-biasing performance booster Ishigaki T, Tsuchiya R, Morita Y, Yoshimoto H, Sugii N, Iwamatsu T, Oda H, Inoue Y, Ohtou T, Hiramoto T, Kimura S |
| 723 - 729 |
High performance 70 nm gate length germanium-on-insulator pMOSFET with high-k/metal gate Romanjek K, Hutin L, Le Royer C, Pouydebasque A, Jaud MA, Tabone C, Augendre E, Sanchez L, Hartmann JM, Grampeix H, Mazzocchi V, Soliveres S, Truche R, Clavelier L, Scheiblin P, Garros X, Reimbold G, Vinet M, Boulanger F, Deleonibus S |
| 730 - 734 |
FDSOI devices with thin BOX and ground plane integration for 32 nm node and below Fenouillet-Beranger C, Denorme S, Perreau P, Buj C, Faynot O, Andrieu F, Tosti L, Barnola S, Salvetat T, Garros X, Casse M, Allain F, Loubet N, Pham-Nguyen L, Deloffre E, Gros-Jean M, Beneyton R, Laviron C, Marin M, Leyris C, Haendler S, Leverd F, Gouraud P, Scheiblin P, Clement L, Pantel R, Deleonibus S, Skotnicki T |
| 735 - 740 |
Folded fully depleted FET using Silicon-On-Nothing technology as a highly W-scaled planar solution Bidal G, Loubet N, Fenouillet-Beranger C, Denorme S, Perreau P, Fleury D, Clement L, Laviron C, Leverd F, Gouraud P, Barnola S, Beneyton R, Torres A, Duluard C, Chapon JD, Orlando B, Salvetat T, Grosjean M, Deloffre E, Pantel R, Dutartre D, Monfray S, Ghibaudo G, Boeuf F, Skotnicki T |
| 741 - 745 |
New floating-body effect in partially depleted SOI pMOSFET due to direct-tunneling current in the partial n plus poly gate Guegan G, Gwoziecki R, Touret P, Raynaud C, Pretet J, Gonnard O, Gouget G, Deleonibus S |
| 746 - 752 |
Method for 3D electrical parameters dissociation and extraction in multichannel MOSFET (MCFET) Dupre C, Ernst T, Bernard E, Guillaumot B, Vulliet N, Coronel P, Skotnicki T, Cristoloveanu S, Ghibaudo G, Faynot O, Deleonibus S |
| 753 - 759 |
Improved sub-threshold slope in short-channel vertical MOSFETs using FILOX oxidation Hakim MMA, Tan L, Buiu O, Redman-White W, Hall S, Ashburn P |
| 760 - 766 |
Performance improvement in narrow MuGFETs by gate work function and source/drain implant engineering Ferain I, Duffy R, Collaert N, van Dal MJH, Pawlak BJ, O'Sullivan B, Witters L, Rooyackers R, Conard T, Popovici M, van Elshocht S, Kaiser M, Weemaes RGR, Swerts J, Jurczak M, Lander RJP, De Meyer K |
| 767 - 772 |
Evaluation of statistical variability in 32 and 22 nm technology generation LSTP MOSFETs Cheng B, Roy S, Brown AR, Millar C, Asenov A |
| 773 - 778 |
A 65 nm test structure for SRAM device variability and NBTI statistics Fischer T, Amirante E, Huber P, Hofmann K, Ostermayr M, Schmitt-Landsiedel D |
| 779 - 785 |
Electron transport through silicon serial triple quantum dots Yamahata G, Tsuchiya Y, Mizuta H, Uchida K, Oda S |
| 786 - 791 |
Impact of a HTO/Al2O3 bi-layer blocking oxide in nitride-trap non-volatile memories Bocquet M, Molas G, Perniola L, Garros X, Buckley J, Gely M, Colonna JP, Grampeix H, Martin F, Vidal V, Toffoli A, Deleonibus S, Ghibaudo G, Pananakakis G, De Salvo B |
| 792 - 797 |
Floating gate technology for high performance 8-level 3-bit NAND flash memory Kim TK, Chang SN, Choi JH |
| 798 - 802 |
Demonstration of a wireless driven MEMS pond skater that uses EWOD technology Mita Y, Li Y, Kubota M, Morishita S, Parkes W, Haworth LI, Flynn BW, Terry JG, Tang TB, Ruthven AD, Smith S, Walton AJ |
| 803 - 808 |
A low-noise single-photon detector implemented in a 130 nm CMOS imaging process Gersbach M, Richardson J, Mazaleyrat E, Hardillier S, Niclass C, Henderson R, Grant L, Charbon E |
| 809 - 813 |
Analysis of the DC-arc behavior of a novel 3D-active fuse vom Dorp J, Berberich SE, Bauer AJ, Ryssel H |