Solid-State Electronics

Solid-State Electronics, Vol.65-66 Entire volume, number list

ISSN: 0038-1101 (Print)

In this Issue (40 articles)

1 - 1	SELECTED PAPERS FROM THE ESSDERC 2010 CONFERENCE Foreword Gamiz F, Godoy A
2 - 8	Effects of corner angle of trapezoidal and triangular channel cross-sections on electrical performance of silicon nanowire field-effect transistors with semi gate-around structure Sato S, Kakushima K, Ahmet P, Ohmori K, Natori K, Yamada K, Iwai H
9 - 15	Dual strained channel CMOS in FDSOI architecture: New insights on the device performance Le Royer C, Casse M, Cooper D, Andrieu F, Weber O, Brevard L, Perreau P, Damlencourt JF, Baudot S, Previtali B, Tabone C, Allain F, Scheiblin P, Rauer C, Figuet C, Aulnette C, Daval N, Nguyen BY, Bourdelle KK, Gyani J, Valenza M
16 - 21	Influence of source/drain formation process on resistance and effective mobility for scaled multi-channel MOSFET Tachi K, Vulliet N, Barraud S, Kakushima K, Iwai H, Cristoloveanu S, Ernst T
22 - 27	Highly scaled (L-g similar to 56 nm) gate-last Si tunnel field-effect transistors with I-ON > 100 mu A/mu m Loh WY, Jeon K, Kang CY, Oh J, Liu TJK, Tseng HH, Xiong WD, Majhi P, Jammy R, Hu CM
28 - 32	Drive current enhancement in p-tunnel FETs by optimization of the process conditions Leonelli D, Vandooren A, Rooyackers R, De Gendt S, Heyns MM, Groeseneken G
33 - 37	Junctionless Nanowire Transistor (JNT): Properties and design guidelines Colinge JP, Kranti A, Yan R, Lee CW, Ferain I, Yu R, Akhavan ND, Razavi P
38 - 44	Boron-layer silicon photodiodes for high-efficiency low-energy electron detection Sakic A, Nanver LK, Scholtes TLM, Heerkens CTH, Knezevic T, van Veen G, Kooijman K, Vogelsang P
45 - 50	Drain-extended MOS transistors capable for operation at 10 V and at radio frequencies Mai A, Rucker H
51 - 56	New mechanism of plasma induced damage on CMOS image sensor: Analysis and process optimization Carrere JP, Oddou JP, Place S, Richard C, Benoit D, Jenny C, Gatefait M, Aumont C, Tournier A, Roy F
57 - 63	Hot-carrier stress induced degradation in Multi-STI-Finger LDMOS: An experimental and numerical insight Poli S, Reggiani S, Baccarani G, Gnani E, Gnudi A, Denison M, Pendharkar S, Wise R
64 - 71	Comparison of strained SiGe heterostructure-on-insulator (0 0 1) and (1 1 0) PMOSFETs: C-V characteristics, mobility, and ON current Pham AT, Zhao QT, Jungemann C, Meinerzhagen B, Mantl S, Soree B, Pourtois G
72 - 80	Half-terahertz silicon/germanium heterojunction bipolar technologies: A TCAD based device architecture exploration Sibaja-Hernandez A, You SZ, Van Huylenbroeck S, Venegas R, De Meyer K, Decoutere S
81 - 87	Strained MOSFETs on ordered SiGe dots Cervenka J, Kosina H, Selberherr S, Zhang JJ, Hrauda N, Stangl J, Bauer G, Vastola G, Marzegalli A, Montalenti F, Miglio L
88 - 93	Multi-Subband Ensemble Monte Carlo simulation of bulk MOSFETs for the 32 nm-node and beyond Sampedro C, Gamiz F, Godoy A, Valin R, Garcia-Loureiro A, Rodriguez N, Tienda-Luna IM, Martinez-Carricondo F, Biel B
94 - 102	3D analytical modelling of subthreshold characteristics in vertical Multiple-gate FinFET transistors Ritzenthaler R, Lime F, Faynot O, Cristoloveanu S, Iniguez B
103 - 107	On the inclusion of Lorentz force effects in TCAD simulations Schoemaker W, Meuris P, Jimenez J, Galy P
108 - 113	Steep-slope nanowire FET with a superlattice in the source extension Gnani E, Reggiani S, Gnudi A, Baccarani G
114 - 122	On the influence of RTA and MSA peak temperature variations on Schottky contact resistances of 6-T SRAM cells Kampen C, Burenkov A, Pichler P, Lorenz J
123 - 129	Computational study of dopant segregated nanoscale Schottky barrier MOSFETs for steep slope, low SD-resistance and high on-current gate-modulated resonant tunneling FETs Afzalian A, Flandre D
130 - 138	Modeling study on carrier mobility in ultra-thin body FinFETs with circuit-level implications Poljak M, Jovanovic V, Suligoj T
139 - 145	A study of N-induced traps due to a nitrided gate in high-kappa/metal gate nMOSFETs and their impact on electron mobility Casse M, Garros X, Weber O, Andrieu F, Reimbold G, Boulanger F
146 - 150	Grain boundary-driven leakage path formation in HfO2 dielectrics Bersuker G, Yum J, Vandelli L, Padovani A, Larcher L, Iglesias V, Porti M, Nafria M, McKenna K, Shluger A, Kirsch P, Jammy R
151 - 156	Test structure and method for the experimental investigation of internal voltage amplification and surface potential of ferroelectric MOSFETs Rusu A, Salvatore GA, Ionescu AM
157 - 162	Resistive switching-like behavior of the dielectric breakdown in ultra-thin Hf based gate stacks in MOSFETs Crespo-Yepes A, Martin-Martinez J, Rothschild A, Rodriguez R, Nafria M, Aymerich X
163 - 169	Drain-current variability in 45 nm bulk N-MOSFET with and without pocket-implants Mezzomo CM, Bajolet A, Cathignol A, Ghibaudo G
170 - 176	Impact of carbon junction implant on leakage currents and defect distribution: Measurement and simulation Roll G, Jakschik S, Burenkov A, Goldbach M, Mikolajick T, Frey L
177 - 183	Rare-earth aluminates as a charge trapping materials for NAND flash memories: Integration and electrical evaluation Suhane A, Cacciato A, Richard O, Arreghini A, Adelmann C, Swerts J, Rothschild O, Van den Bosch G, Breuil L, Bender H, Jurczak M, Debusschere I, Kittl JA, De Meyer K, Van Houdt J
184 - 190	Quasi-planar bulk CMOS technology for improved SRAM scalability Shin C, Tsai CH, Wu MH, Chang CF, Liu YR, Kao CY, Lin GS, Chiu KL, Fu CS, Tsai CT, Liang CW, Nikolic B, Liu TJK
191 - 196	A method to analyze the impact of fast-recovering NBTI degradation on the stability of large-scale SRAM arrays Drapatz S, Hofmann K, Georgakos G, Schmitt-Landsiedel D
197 - 204	Carbon-doped GeTe: A promising material for Phase-Change Memories Beneventi GB, Perniola L, Sousa V, Gourvest E, Maitrejean S, Bastien JC, Bastard A, Hyot B, Fargeix A, Jahan C, Nodin JF, Persico A, Fantini A, Blachier D, Toffoli A, Loubriat S, Roule A, Lhostis S, Feldis H, Reimbold G, Billon T, De Salvo B, Larcher L, Pavan P, Bensahel D, Mazoyer P, Annunziata R, Zuliani P, Boulanger F
205 - 210	Substrate bias dependency of sense margin and retention in bulk FinFET 1T-DRAM cells Collaert N, Aoulaiche M, De Keersgieter A, De Wachter B, Altimime L, Jurczak M
211 - 218	Visible and NIR integrated Phototransistors in CMOS technology Kostov P, Gaberl W, Zimmermann H
219 - 225	Effect of the substrate on RF power-handling capability of micro-electromechanical capacitive switches Solazzi F, Palego C, Halder S, Hwang JCM, Faes A, Mulloni V, Margesin B, Farinelli P, Sorrentino R
226 - 233	Tunneling FETs on SOI: Suppression of ambipolar leakage, low-frequency noise behavior, and modeling Wan J, Le Royer C, Zaslavsky A, Cristoloveanu S
234 - 239	Abrupt switch based on internally combined band-to-band and barrier tunneling mechanisms Lattanzio L, Biswas A, De Michielis L, Ionescu AM
240 - 245	Field-coupled computing: Investigating the properties of ferromagnetic nanodots Kiermaier J, Breitkreutz S, Ju X, Csaba G, Schmitt-Landsiedel D, Becherer M
246 - 249	Performance trade-offs in polysilicon source-gated transistors Sporea RA, Trainor MJ, Young ND, Guo X, Shannon JM, Silva SRP
250 - 255	Transient effects in partial-RESET programming of phase-change memory cells Braga S, Cabrini A, Torelli G
256 - 262	SOI 1T-DRAM cells with variable channel length and thickness: Experimental comparison of programming mechanisms Hubert A, Bawedin M, Guegan G, Ernst T, Faynot O, Cristoloveanu S