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SELECTED PAPERS FROM THE ESSDERC 2011 CONFERENCE Foreword Ostling M, Malm BG |
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Experimental study of electron mobility characterization in direct contact La-silicate/Si structure based nMOSFETs Kawanago T, Lee Y, Kakushima K, Ahmet P, Tsutsui K, Nishiyama A, Sugii N, Natori K, Hattori T, Iwai H |
7 - 12 |
Impact of oxidation and reduction annealing on the electrical properties of Ge/La2O3/ZrO2 gate stacks Henkel C, Hellstrom PE, Ostling M, Stoger-Pollach M, Bethge O, Bertagnolli E |
13 - 18 |
Enhancement of FinFET performance using 25-nm-thin sidewall spacer grown by atomic layer deposition Endo K, Ishikawa Y, Matsukawa T, Liu YX, O'uchi S, Sakamoto K, Tsukada J, Yamauchi H, Masahara M |
19 - 24 |
On the efficiency of stress techniques in gate-last n-type bulk FinFETs Eneman G, Collaert N, Veloso A, De Keersgieter A, De Meyer K, Hoffmann TY, Horiguchi N, Thean A |
25 - 31 |
Comparative study of circuit perspectives for multi-gate structures at sub-10 nm node Lacord J, Huguenin JL, Monfray S, Coquand R, Skotnicki T, Ghibaudo G, Boeuf F |
32 - 37 |
Parasitic bipolar impact in 32 nm undoped channel Ultra-Thin BOX (UTBOX) and biased Ground Plane FDSOI high-k/metal gate technology Fenouillet-Beranger C, Perreau P, Boulenc P, Tosti L, Barnola S, Andrieu F, Weber O, Beneyton R, Perrot C, de Buttet C, Abbate F, Campidelli Y, Pinzelli L, Gouraud P, Margain A, Peru S, Bourdelle KK, Nguyen BY, Boedt F, Poiroux T, Faynot O, Skotnicki T, Boeuf F |
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Understanding device performance by incorporating 2D-carrier profiles from high resolution scanning spreading resistance microscopy into device simulations Nazir A, Eyben P, Clarysse T, Hellings G, Schulze A, Mody J, De Meyer K, Bender H, Vandervorst W |
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Nanoscale carrier injectors for high luminescence Si-based LEDs Piccolo G, Kovalgin AY, Schmitz J |
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PNP PIN bipolar phototransistors for high-speed applications built in a 180 nm CMOS process Kostov P, Gaberl W, Hofbauer M, Zimmermann H |
58 - 63 |
ALD high-k layer grating couplers for single and double slot on-chip SOI photonics Naiini MM, Henkel C, Mahn GB, Ostling M |
64 - 70 |
Comprehensive investigation of the impact of lateral charge migration on retention performance of planar and 3D SONOS devices Maconi A, Arreghini A, Compagnoni CM, Van den Bosch G, Spinelli AS, Van Houdt J, Lacaita AL |
71 - 76 |
CMOS compatible self-aligned S/D regions for implant-free InGaAs MOSFETs Czornomaz L, El Kazzi M, Hopstaken M, Caimi D, Machler P, Rossel C, Bjoerk M, Marchiori C, Siegwart H, Fompeyrine J |
77 - 84 |
Transient electro-thermal characterization of Si-Ge heterojunction bipolar transistors Sahoo AK, Weiss M, Fregonese S, Malbert N, Zimmer T |
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The electron-hole bilayer tunnel FET Lattanzio L, De Michielis L, Ionescu AM |
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Virtually dopant-free CMOS: Midgap Schottky-barrier nanowire field-effect-transistors for high temperature applications Wessely F, Krauss T, Schwalke U |
97 - 101 |
Tunneling field-effect transistor with a strained Si channel and a Si0.5Ge0.5 source Zhao QT, Yu WJ, Zhang B, Schmidt M, Richter S, Buca D, Hartmann JM, Luptak R, Fox A, Bourdelle KK, Mantl S |
102 - 107 |
Compensation of externally applied mechanical stress by stacking of ultrathin chips Endler S, Rempp H, Harendt C, Burghartz JN |
108 - 113 |
AlGaN/GaN power amplifiers for ISM applications Krausse D, Benkhelifa F, Reiner R, Quay R, Ambacher O |
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Accumulation-mode gate-all-around si nanowire nMOSFETs with sub-5 nm cross-section and high uniaxial tensile strain Najmzadeh M, Bouvet D, Grabinski W, Sallese JM, Ionescu AM |
121 - 125 |
Study on dual-lateral-gate suspended-body single-walled carbon nanotube field-effect transistors Cao J, Ionescu AM |
126 - 133 |
PureGaB p(+)n Ge diodes grown in large windows to Si with a sub-300 nm transition region Sammak A, Qi L, de Boer WB, Nanver LK |
134 - 141 |
Two-stage trigger silicon-controller rectifier (SCR) for radio-frequency (RF) input and output protections in nanometer technologies Lee JH, Wu YH, Huang SC, Lee YH, Chen KH |