Solid-State Electronics

Solid-State Electronics, Vol.46, No.3 Entire volume, number list

ISSN: 0038-1101 (Print)

In this Issue (21 articles)

313 - 313	Special issue on ultimate integration of silicon (ULIS 2000) - Foreword Balestra F
315 - 320	Design considerations for CMOS near the limits of scaling Frank DJ, Taur Y
321 - 328	Ultra-thin gate oxide reliability projections Weir BE, Alam MA, Silverman PJ, Baumann F, Monroe D, Bude JD, Timp GL, Hamad A, Ma Y, Brown MM, Hwang D, Sorsch TW, Ghetti A, Wilk GD
329 - 336	Continued growth in CMOS beyond 0.10 mu m Sugii T, Momiyama Y, Goto K
337 - 342	Secondary impact ionization and device aging in deep submicron MOS devices with various transistor architectures Marchand B, Cretu B, Ghibaudo G, Balestra F, Blachier D, Leroux C, Deleonibus S, Guegan G, Reimbold G, Kubicek S, DeMeyer K
343 - 348	A 0.10 mu m buried p-channel MOSFET with through the gate boron implantation and arsenic tilted pocket Guegan G, Deleonibus S, Caillat C, Tedesco S, Dal'zotto B, Heitzmann M, Nier ME, Mur P
349 - 352	A 20 nm physical gate length NMOSFET with a 1.2 nm gate oxide fabricated by mixed dry and wet hard mask etching Caillat C, Deleonibus S, Guegan G, Heitzmann M, Nier ME, Tedesco S, Dal'zotto B, Martin F, Mur P, Papon AM, Lecarval G, Previtali B, Toffoli A, Allain F, Biswas S, Jourdan F, Fugier P, Dichiaro JL
353 - 360	Development of a RF large signal MOSFET model, based on an equivalent circuit, and comparison with the BSIM3v3 compact model Vandamme EP, Schreurs D, van Dinther C, Badenes G, Deferm L
361 - 366	1/f noise measurements in n-channel MOSFETs processed in 0.25 mu m technology - Extraction of BSIM3v3 noise parameters Allogo YA, de Murcia M, Vildeuil JC, Valenza M, Llinares P, Cottin D
367 - 371	Reliability of ultra-thin film deep submicron SIMOX nMOSFETs Potavin O, Haendler S, Jomaah J, Balestra F, Raynaud C
373 - 378	Fringing fields in sub-0.1 mu m fully depleted SOI MOSFETs: optimization of the device architecture Ernst T, Tinella C, Raynaud C, Cristoloveanu S
379 - 386	0.25 mu m fully depleted SOI MOSFETs for RF mixed analog-digital circuits, including a comparison with partially depleted devices with relation to high frequency noise parameters Vanmackelberg M, Raynaud C, Faynot O, Pelloie JL, Tabone C, Grouillet A, Martin F, Dambrine G, Picheta L, Mackowiak E, Llinares P, Sevenhans J, Compagne E, Fletcher G, Flandre D, Dessard V, Vanhoenacker D, Raskin JP
387 - 391	Enhancement of device performance in vertical sub-100 nm MOS devices due to local channel doping Fink C, Anil KG, Geiger H, Hansch W, Kaesen F, Schulze J, Sulima T, Eisele I
393 - 398	On the origin of the LF noise in Si/Ge MOSFETs Ghibaudo G, Chroboczek J
399 - 405	Stress induced leakage current under pulsed voltage stress Cester A, Paccagnella A, Ghidini G
407 - 416	Electrical characterization and modeling of MOS structures with an ultra-thin oxide Clerc R, De Salvo B, Ghibaudo G, Reimbold G, Pananakakis G
417 - 422	Modeling of stress-induced leakage current and impact ionization in MOS devices Ielmini D, Spinelli AS, Lacaita AL, Ghidini G
423 - 428	Simulation of polysilicon quantization and its effect on n- and p-MOSFET performance Spinelli AS, Pacelli A, Lacaita AL
429 - 434	Analytical and numerical study of the impact of HALOs on short channel and hot carrier effects in scaled MOSFETs Zanchetta S, Todon A, Abramo A, Selmi L, Sangiorgi E
435 - 444	Quantum transport in a cylindrical sub-0.1 mu m silicon-based MOSFET Balaban SN, Pokatilov EP, Fomin VM, Gladilin VN, Devreese JT, Magnus W, Schoenmaker W, Van Rossum M, Soree B
445 - 449	Computational investigation of the accuracy of constant-dC scanning capacitance microscopy for ultra-shallow doping profile characterization Ciampolini L, Ciappa M, Malberti P, Fichtner W